The present invention relates to content addressable memory (CAM) arrays. More specifically, the present invention relates to dynamic random-access-memory (DRAM) CAM arrays.
Semiconductor memory devices fall into two broad categories: read only memory (ROM) devices, and read-write or xe2x80x9crandom accessxe2x80x9d memory (RAM) devices. ROM (e.g., EPROM or EEPROM) devices are non-volatile devices primarily used to store data when system power is turned off. In contrast, RAM devices temporarily store data that is used during system operation. RAM devices are typically volatile in that the data stored in a RAM device is lost when power is turned off. RAM devices are roughly divided into two types: static random access memory (SRAM) devices, and dynamic random access memory (DRAM) devices.
An SRAM device consists of a basic bistable flipflop circuit that needs only an applied DC current to retain a data value. To store a logic xe2x80x9c1xe2x80x9d data value (bit), the bistable flipflop is biased into a first stable state, and to store a logic xe2x80x9c0xe2x80x9d data value, the bistable flipflop is biased into its second stable state. The bistable flipflop maintains the first or second stable state until an opposite biasing voltage is applied that xe2x80x9cflipsxe2x80x9d the bistable flipflop from the first to the second (or the second to the first) stable state. While this stable data storage provides certain advantages, a main disadvantage of SRAM cells is their relatively large size due to the multiple (typically six or more) transistors required to form and access the bistable flipflop circuit.
In contrast to SRAM cells, a DRAM cell stores a data value as a charge on a capacitor or wire. The main advantage of most DRAM cells is that the basic DRAM memory cell requires only a single transistor and a capacitor, thereby making DRAM cells significantly smaller and less expensive to produce than SRAM cells. Other DRAM memory cells include several transistors and are able to store a data value without special fabrication steps needed to produce the capacitor of the single transistor cell. The main disadvantage of DRAM cells is that the stored data values decay over time, thereby requiring refresh circuitry that reads and rewrites (refreshes) the stored data values before they are lost. The time required to perform this refresh operation often reduces the effectiveness of any logic operation that utilizes the data values stored in the DRAM cells.
Conventional RAM arrays include RAM cells arranged in rows and columns, and addressing circuitry that accesses a selected row of RAM cells using address data corresponding to the physical address of the RAM cells. That is, data words stored in the rows of conventional RAM cells are accessed by applying address signals to the RAM array input terminals. In response to each unique set of address signals, a RAM array outputs a data word that is read from a portion of the RAM array designated by the address.
Unlike conventional RAM arrays, content addressable memory (CAM) arrays include memory cells that are addressed in response to their content, rather than by a physical address within a RAM array. Specifically, a CAM array receives a data value that is compared with all of the data values stored in the rows of the CAM array. In response to each unique data value applied to the CAM array input terminals, the rows of CAM cells within the CAM array assert or de-assert associated match signals indicating whether or not one or more data values stored in the CAM cell rows match the applied data value. CAM arrays are useful in many applications, such as search engines.
Similar to conventional RAM devices, CAM devices can either be formed as DRAM CAM devices, in which data values are stored using capacitors, or SRAM CAM devices, in which data values are stored using bistable flipflop circuits. Also similar to conventional RAM devices, DRAM CAM devices provide an advantage in that they are typically smaller than SRAM CAM devices.
FIG. 1(A) is a circuit diagram showing a conventional dynamic (DRAM) CAM cell 10, which is formed by six transistors Q1 through Q6. During a data write operation (or during the write phase of a refresh operation), a data value to be stored is written to dynamic storage nodes a and b (depicted by dashed capacitive plates) by applying a true (e.g., logic xe2x80x9c1xe2x80x9d or VCC) data signal and a complement (e.g., logic xe2x80x9c0xe2x80x9d or ground) data signal to bit lines B and B# (the xe2x80x9c#xe2x80x9d is used herein to designate complement), and then applying a high voltage signal on word line W. The high voltage on word line W turns on transistor Q5 and Q6, thereby passing the data signals to dynamic storage nodes a and b.
Subsequent to storing a data value in DRAM CAM cell 10, a match (comparison) operation is performed by precharging a match line M and transmitting a data value to be compared onto bit lines B and B#. A no-match condition is detected when match line M is discharged to ground through the signal path formed by transistors Q1 and Q2, or through the signal path formed by transistors Q3 and Q4. For example, when the stored data value at node a and the applied data value transmitted on bit line B are both logic xe2x80x9c1xe2x80x9d, then both transistors Q1 and Q2 are turned on to discharge match line M to ground. When a match condition occurs, match line M remains in its precharged state (i.e., no signal path is formed by transistors Q1 through Q4).
A first problem with DRAM CAM cell 10 is that, in order to refresh the dynamic storage nodes a and b, a refresh cycle must be inserted between the match operations. This refresh operation requires turning on the word line W such that the data values stored at dynamic nodes a and b are applied to bit lines B and B# through transistors Q5 and Q6, sensing the data values on bit lines B and B#, and then rewriting these sensed data values back to dynamic nodes a and b through transistors Q5 and Q6. Because the bit lines B and B# are used during the refresh operation and during xe2x80x9clogicxe2x80x9d (i.e., match) operations, the match operations are undesirably delayed until the refresh operation is completed, thereby making performance of DRAM CAM cell 10 undesirably slow.
A second problem associated with DRAM CAM cell 10 is that, even if separate bit lines are provided to allow simultaneous refresh and match operations, the read phase of the refresh operation can be disturbed by the simultaneous match operation. When conventional DRAM cells are read, the read data values are typically transmitted to associated bit lines during xe2x80x9cquitexe2x80x9d periods in which switching noise in a DRAM array does not cause a loss of the read data values. However, by allowing simultaneous match operations during the read phase of the refresh operation, it is possible to lose the read data values. Accordingly, providing separate bit lines does not necessarily facilitate simultaneous read and match operations.
A third problem associated with DRAM CAM cell 10 is that, due to the read phase of the refresh operation, the number of cells in each column of a DRAM CAM array must be minimized. That is, the length and, hence, the capacitance of bit lines B and B# increases with the number of DRAM CAM cells arranged in a column that are connected to these lines. Because the data values are partially decayed before being transmitted from each DRAM CAM cell onto bit lines B and B#, this capacitance can generate read phase errors if bit lines B and B# are too long. By limiting the number of DRAM CAM cells in each column, the number of independent blocks of DRAM memory cells is increased, thereby requiring more space for control circuitry and increasing the overall size and cost of the DRAM CAM circuit.
FIG. 1(B) is a circuit diagram showing a dual port DRAM CAM cell 20 that is disclosed in U.S. Pat. No. 5,642,320. Dual port DRAM CAM cell 20 overcomes the first problem described above by providing a seventh transistor Q7 and an eight transistor Q8 that are connected to a second set of dedicated lines (i.e., data lines D and D#), and are turned on by a select line S during refresh operations. Accordingly, match operations and refresh operations can be performed simultaneously. However, dual port DRAM CAM cell 20 fails to address the second and third problems (discussed above) in that, because data is read from dynamic nodes a and b during the read phase of the refresh operation, this data can be disturbed by simultaneously performed match operations. Further, the required read phase of the refresh operation limits the number of cells in each column for the reasons explained above, thereby increasing overall size and cost of a CAM circuit made up of DRAM CAM cells 20.
Accordingly, what is needed is a DRAM circuit in which logic operations are not delayed or otherwise disrupted by the refresh operation.
The present invention is directed to DRAM circuits that overcome the problems associated with conventional DRAM circuits (e.g., DRAM CAM arrays) by providing first and second associated DRAM arrays that store essentially identical data values. The first DRAM array is used solely for refresh operations (and data read operations), and the second DRAM array is utilized to perform logic operations (e.g., match operations). During the read phase of a refresh operation, data values are read only from the first DRAM array by a refresh circuit, and during a subsequent write phase of the refresh operation, data values are written from the refresh circuit to both the first and the second DRAM arrays. Because data values are only written to (not read from) the second DRAM array, logic operations performed using the second DRAM array are not delayed or otherwise disrupted during the read phase of the refresh operation. Accordingly, the present invention avoids the problems associated with conventional DRAM arrays.
In addition, because the data values stored in the first DRAM array are copied into the second DRAM array, the data stored in the second DRAM array can be read during read operations without interrupting other logic functions by reading the data stored in the first DRAM array. Write operations are performed by simultaneously transmitting a data value to associated dram cells located in both the first and second DRAM arrays.
In accordance with a disclosed specific embodiment of the present invention, a DRAM CAM circuit includes a DRAM CAM array for performing match (comparison) operations, and an associated DRAM memory array that stores the same data values stored in the DRAM CAM array. Data values are read from the DRAM memory array during a read phase of a refresh operation, and then written both to the DRAM memory array and to a DRAM CAM array during a write phase of the refresh operation. Accordingly, the DRAM CAM array is continuously refreshed without reading the data values stored in the DRAM CAM array during the refresh operation. Further, the data values written from the refresh circuit to the DRAM CAM array are transmitted on dedicated bit lines, thereby allowing the simultaneous performance of data match operations by the DRAM CAM array. Moreover, by utilizing a separate DRAM memory array to refresh the DRAM CAM cell, the size of each DRAM CAM cell is minimized, thereby minimizing the length of, for example, the match lines, thereby reducing capacitance and power loss.
The present invention will be more fully understood in view of the following description and drawings.